1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including device supplying voltages higher than a power supply voltage to an internal circuit.
2. Description of the Related Art
In recent years, demand for the low power consumption of semiconductor circuits is becoming increasingly severe, and the level of the employed power supply voltage is being reduced accordingly. In the meantime, the operating speed of the transistors in the semiconductor circuits is lowered with the reduction in the operating voltage. Consequently, portions of the circuits where a particularly high speed operation is required are frequently operated with voltages obtained by boosting the power supply voltage. For example, when the read voltage applied to the gate of a transistor constituting the memory cell is reduced depending on the power supply voltage, the read rate is reduced accordingly. A means for resolving such a problem is disclosed in Japanese Patent Laid-open No. Hei 2-3192. Referring to FIG. 10, this conventional method will be described in detail.
A decoder circuit 901 employed in a flash EEPROM comprises a selection circuit, a voltage isolation circuit, and a charging circuit.
The selection circuit comprises a NAND gate 907, a NOT gate 908, and N-channel MOS transistors 949 and 950. The NAND gate 907 receives an address 906, its output is connected to the NOT gate 908 and the gate terminal of the N-channel MOS transistor 950, and the output of the NOT gate 908 is connected to the gate terminal of the N-channel MOS transistor 949. An address 947 is input to the drain terminal of the N-channel MOS transistor 949, and the junction of the source terminal of the N-channel MOS transistor 949 and the drain terminal of the N-channel MOS transistor 950 is served as the output of the selection circuit.
The voltage isolation circuit is formed of an N-channel MOS transistor 909, its gate terminal is connected to a power supply 917, its source terminal is connected to the output of the selection circuit, and its drain terminal is served as the output of the voltage isolation circuit.
The charging circuit comprises N-channel MOS transistors 942 and 943, and capacitors C0 and C1. A terminal 948 supplies a charging voltage Vpp, and a terminal 946 which supplies a clock .phi. for write charging is connected to one end of the capacitor C1 and the source terminal of an N-channel MOS transistor 942. An N-channel MOS transistor 949 is connected to one end of the capacitor C0, the source terminal of an N-channel MOS transistor 943, and the output of the voltage isolation circuit, where the source terminal of the transistor 943 is served as the output of the decoder circuit 901.
The charging voltage Vpp is generated from the power supply voltage by means of a booster circuit. An example of the booster circuit is shown in FIG. 6. In this booster circuit, N-channel MOS transistors 606, and 608, with their respective gate terminals and drain terminals connected separately, are connected in series, and one ends of capacitors 607 are connected to the drain terminals of the respective transistors 606 while the other ends of the capacitors 607 are alternately supplied with clocks generated stepwise, via logical gates 609, 610, and 611, from the clock .phi. supplied through a terminal 601. The charging voltage Vpp is generated from the power supply voltage by controlling the output voltage 603 of the series connection of the transistors 606 and 608 with the output of the series connection of N-channel MOS transistors 605. It is to be noted that the charging circuit is activated when a signal READ supplied to a terminal 602 is at a logically high level "H".
Returning to FIG. 10, the outputs of respective decoder circuits are connected to corresponding word lines X0 and Xn of a memory array 902 formed by arranging memory cells 914 in an array form. The source terminals of all transistors in the memory array 902 are connected in common to a terminal 939 to be supplied with a voltage Vs. The columns of the memory array 902 are connected to a sense amplifier 903 as digit lines D0 to Dm, and the storage contents of the memory cells are output as a sense output 913.
Next, referring to FIG. 11, the operation of the device in FIG. 10 will be described.
When all the inputs to the NAND gate 907 go to the power supply voltage with the changes in the address 906, the output of the gate 907 goes to the ground potential (FIG. 111), and in response to this the output of the NOT gate 908 goes to the power supply voltage (FIG. 112). Then, the N-channel MOS transistor 950 is deenergized, and the N-channel MOS transistor 949 is energized. I n addition, since the address 947 is at "H" by being selected, a word line 911 is charged up to Vdd-Vtn 909 via an N-channel MOS transistor 909, where Vdd is the voltage of the power supply 917 and Vtn 909 is the threshold voltage of the N-channel MOS transistor 909 (FIGS. 113 and 114). After this, when a high voltage pulse is given by a change in the charging voltage Vpp, the potential of the word line 911 is raised by C0/(C0+CE)*Vpp from Vdd-Vtn 909 (FIG. 115), where CE is the parasitic capacitance of the word line 911. As a result, the potential of a digit line 912 is changed by the storage contents of a memory cell selected due to the address change (FIG. 116), and the potential of the digit line 912 detected and amplified by the sense amplifier 903 is output to the sense output 913 (FIG. 117). Since the voltage higher than the power supply voltage can be applied to the word line as in the above, it is possible to obtain a sufficiently high current in the memory cell and improve the operating speed of the memory even when the power supply voltage Vdd is low. Moreover, even when the power supply voltage is lower than the threshold voltage of the memory cell, it is possible to correctly read the storage contents.
However, the conventional technique described above has a problem in that in giving a voltage higher than the power supply voltage to the word line, the high voltage pulse generated from the power supply voltage by means of the booster circuit is output to the terminal 948 in FIG. 10. Namely, the pulse supplied to the terminal 948 in FIG. 10 has to charge and discharge the parasitic capacitance of the terminal 948 for each rise and fall of the pulse is decreased, which results in the reduction of the read rate of data from the memory cells. In order to prevent such a reduction in the read rate it is necessary to use a booster circuit having a large current supply capability to charge the terminal 948 rapidly to the voltage Vpp. Since the booster circuit carries out voltage step-up by transferring the charge by means of the capacitors and the clocks, capacitors with large capacitances are required for the booster circuit in order to realize a booster circuit with high current driving capability. That is, a booster circuit having a large current supply capability causes an increase in the occupied area on the semiconductor substrate. This problem is the more conspicuous as the power supply voltage becomes lower.
Moreover, since the potential of the selected word line is boosted by means of a coupling capacitor, it is necessary to provide the capacitor C0 to all the word lines, which results in an increased area on the semiconductor substrate.
Furthermore, the voltage of the boosted word line becomes Vpp+(Vdd-Vtn). Consequently, even if one manages to get a voltage Vpp which is independent of the power supply voltage Vdd, the boosted voltage will eventually be dependent upon Vdd according to the above expression. In addition, the power supply voltage Vdd fluctuates due to the noises generated by the operation of other circuits, so that the voltage supplied to the word line also fluctuates, which becomes the cause of the malfunctions.